Design and Development of Reversible Half adder using an 8*8 reversible logic gate
Keywords:
Reversible gate, CMOS, garbage output.
Abstract
A digital logic circuit that adds two binary single-bit integers is called a half adder. In many different types of processors, adders are commonly used to perform arithmetic and logical operations. In this study, we examine how a half adder works using a recently designed CMOS logic gate. The suggested design and the existing system have been compared using garbage output. The circuits are simulated using the MATLAB program.
References
1. Anand, R. K., Singh, K., Verma, P., & Thakur, A. (2015). Design of area and power efficient half adder using transmission gate. International Journal of Research in Engineering and Technology, 4, 122–125.
2. Divyadharshini, A. (2014). CMOS logic styles based on double gate MOSFETs are used to create a full adder. International Journal of Scientific & Engineering Research, 5, 210–216.
3. Kumar, B., Mittal, P., Baliga, A. K., Rathod, A. P. S., & Lakhera, P. (2015). Comparing the performance of demultiplexers based on CMOS logic configuration and pass transistors. In Proceedings of the International Conference on Automation and Communication in Computing (pp. 1433–1437).
4. Kumar, P., Bhandari, N. S., Bhargav, L., Rathi, R., & Yadav, S. C. (2017). Pass transistor-based low power and area efficient half adder design and performance parameter comparison. In Proceedings of the International Conference on Automation, Communication, and Computing (pp. 1477–1482).
5. Kumawat, R., Srinivasulu, A., & Saini, J. K. (2019). A low power, high speed CNTFET full adder cell with overflow detection. Micro and Nanosystems, 80–87.
6. Manisha, A. (2014). A comparison of static CMOS logic-style full adders. International Journal of Research in Engineering and Technology, 3, 489–494.
7. Mittal, P., Kumar, B., Yadav, S. C., & Rathod, A. P. S. (2014). Pass transistor logic is used in low power VLSI design. In Proceedings of the National Technical Expo. NRDC, New Delhi, & Graphic Era University.
8. Naseri, H., & Timarchi, S. (2018). Low-power and fast full adder by investigating novel XOR and XNOR gates. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1–13.
9. Praveen, B., & Vinay Kumar, S. B. (2012). 2n:1 transistor-based reversible multiplexer. International Journal of Computational Engineering Research, 2, 182–189.
10. Pyla, R., Santosh Kumar, Y. L. V., & Raghu Vamsi, H. K. (2019). Full adder designs using low power full swing XOR and XNOR structures. International Journal of Innovative Technology and Exploring Engineering, 198–203.
11. Sharma, I., & Mehra, R. (2016). Half-subtractor delay analysis with CMOS and pass transistor logic. International Journal of Computer Applications, 141, 12–16.
12. Somasekhar Varma, N., Srilakshmi, K., & Syamala, Y. (2013). Gate diffusion input is used in the design of low power CMOS logic devices. International Journal of VLSI Design & Communication Systems, 4, 5–8.
2. Divyadharshini, A. (2014). CMOS logic styles based on double gate MOSFETs are used to create a full adder. International Journal of Scientific & Engineering Research, 5, 210–216.
3. Kumar, B., Mittal, P., Baliga, A. K., Rathod, A. P. S., & Lakhera, P. (2015). Comparing the performance of demultiplexers based on CMOS logic configuration and pass transistors. In Proceedings of the International Conference on Automation and Communication in Computing (pp. 1433–1437).
4. Kumar, P., Bhandari, N. S., Bhargav, L., Rathi, R., & Yadav, S. C. (2017). Pass transistor-based low power and area efficient half adder design and performance parameter comparison. In Proceedings of the International Conference on Automation, Communication, and Computing (pp. 1477–1482).
5. Kumawat, R., Srinivasulu, A., & Saini, J. K. (2019). A low power, high speed CNTFET full adder cell with overflow detection. Micro and Nanosystems, 80–87.
6. Manisha, A. (2014). A comparison of static CMOS logic-style full adders. International Journal of Research in Engineering and Technology, 3, 489–494.
7. Mittal, P., Kumar, B., Yadav, S. C., & Rathod, A. P. S. (2014). Pass transistor logic is used in low power VLSI design. In Proceedings of the National Technical Expo. NRDC, New Delhi, & Graphic Era University.
8. Naseri, H., & Timarchi, S. (2018). Low-power and fast full adder by investigating novel XOR and XNOR gates. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1–13.
9. Praveen, B., & Vinay Kumar, S. B. (2012). 2n:1 transistor-based reversible multiplexer. International Journal of Computational Engineering Research, 2, 182–189.
10. Pyla, R., Santosh Kumar, Y. L. V., & Raghu Vamsi, H. K. (2019). Full adder designs using low power full swing XOR and XNOR structures. International Journal of Innovative Technology and Exploring Engineering, 198–203.
11. Sharma, I., & Mehra, R. (2016). Half-subtractor delay analysis with CMOS and pass transistor logic. International Journal of Computer Applications, 141, 12–16.
12. Somasekhar Varma, N., Srilakshmi, K., & Syamala, Y. (2013). Gate diffusion input is used in the design of low power CMOS logic devices. International Journal of VLSI Design & Communication Systems, 4, 5–8.
Published
2024-01-20
How to Cite
Prateeksha Yadav, Jyoti Mishra, & Raj Kumar Tiwari. (2024). Design and Development of Reversible Half adder using an 8*8 reversible logic gate. Revista Electronica De Veterinaria, 25(1), 4696 - 4700. Retrieved from https://www.veterinaria.org/index.php/REDVET/article/view/2481
Issue
Section
Articles
