FPGA Implementation of Modulo 2n ±1 Adder-Subtractor
Keywords:
Modulo Arithmetic, Modulo 2n 1, modulo 2n-1, Redundant Number Systems, Diminished-One Representation, LUTs, Timing Analysis, Area Optimization, Delay Optimization, Prefix Adder, CSA, Parallel Prefix Structures, Logic Slices.
Abstract
Arithmetic modulo operators, especially those involving 2n + 1, have wide-ranging applications in fields like pseudorandom number generation, cryptography, and digital signal processing (DSP). These modulo operations are particularly useful in the Residue Number System (RNS). This work presents the design of a modulo 2n ± 1 adder-subtractor using a parallel prefix adder. The design leverages two numerical representations: weighted-one and diminished-one. After developing the adder-subtractor, it is implemented on an FPGA to evaluate its performance. A detailed comparison has been conducted between the two representations, focusing on area utilization and execution time.
References
[1] Bhaskar Gaur, and Himanshu Thapliyal, “Novel Optimized Designs of Modulo 2n+1 Adder for Quantum Computing”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems ( Volume: 32, Issue: 9, pp. 1759 – 1763, September 2024)
[2] Yamani, Sudha & Kudulla, H K Raghu & Bhavani, “Area Efficient Sparse-4 Diminished-1 Modulo 2n+1 Adder”, IEEE Wireless Antenna and Microwave Symposium, (2024)
[3] Prabir Saha, Rekib Uddin Ahmed, and Sheba Thabah, “Design and Implementation of Multi-operand 2n-1, 2n, and 2n+1 Modulo Set Adder”, Advances in Communication, Devices and Networking , pp.1-8, August (2021)
[4] Subodh Kumar Singhal, B. K. Mohanty, Sujit Kumar Patel, and Gaurav Saxena, “Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder”, Journal of Circuits, Systems and Computers, vol. 29, No. 12, July (2020)
[5] Constantinos Efstathiou, Kiamal Pekmestzi, and Nikolaos Moshopoulos, “On the Diminished-1 Modulo 2n+1 Addition and Subtraction”, Journal of Circuits, Systems and Computers, vol. 29, No. 05, July (2019)
[6] G H Asha, and J Uday, “Implementation of 32-bit area-efficient hybrid modulo 2n+1 adder and multiplier”, International Conference on Control, Instrumentation, Communication and Computational Technologies, July (2014)
[7] Haridimos T. Vergos, and Giorgos Dimitrakopoulos, “On Modulo 2n + 1 Adder Design” Feb.(2012)
[8] H.T. Vergos and C. Efstathiou, “Efficient Modulo 2n+1 Adder Architectures,” Integration, the VLSI J., vol. 42, no. 2, pp. 149-157,Feb. (2009).
[9] G. Jaberipur and B. Parhami, “Unified Approach to the Design of Modulo-(2n - 1) Adders Based on Signed-LSB Representation of Residues,” Proc. 19th IEEE Symp. Computer Arithmetic, pp. 57-64,(2009).
[10] H. T. Vergos and D. Bakalis, “On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components”(2008)
[11] R. Zimmerman, “Efficient VLSI Implementation of Modulo 2n 1 Addition and Multiplication,” Proc. 14th IEEE Symp. ComputerArithmetic, pp. 158-167, Apr. (1999).
[12] Singh, A., Anand, V., Singh, S., & Sharma, A. Examining GIS Methodologies and Their Diverse Applications in Solid Waste Management. Journal of Survey in Fisheries Sciences, 10(1), 1442-1447. (2023)
[2] Yamani, Sudha & Kudulla, H K Raghu & Bhavani, “Area Efficient Sparse-4 Diminished-1 Modulo 2n+1 Adder”, IEEE Wireless Antenna and Microwave Symposium, (2024)
[3] Prabir Saha, Rekib Uddin Ahmed, and Sheba Thabah, “Design and Implementation of Multi-operand 2n-1, 2n, and 2n+1 Modulo Set Adder”, Advances in Communication, Devices and Networking , pp.1-8, August (2021)
[4] Subodh Kumar Singhal, B. K. Mohanty, Sujit Kumar Patel, and Gaurav Saxena, “Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder”, Journal of Circuits, Systems and Computers, vol. 29, No. 12, July (2020)
[5] Constantinos Efstathiou, Kiamal Pekmestzi, and Nikolaos Moshopoulos, “On the Diminished-1 Modulo 2n+1 Addition and Subtraction”, Journal of Circuits, Systems and Computers, vol. 29, No. 05, July (2019)
[6] G H Asha, and J Uday, “Implementation of 32-bit area-efficient hybrid modulo 2n+1 adder and multiplier”, International Conference on Control, Instrumentation, Communication and Computational Technologies, July (2014)
[7] Haridimos T. Vergos, and Giorgos Dimitrakopoulos, “On Modulo 2n + 1 Adder Design” Feb.(2012)
[8] H.T. Vergos and C. Efstathiou, “Efficient Modulo 2n+1 Adder Architectures,” Integration, the VLSI J., vol. 42, no. 2, pp. 149-157,Feb. (2009).
[9] G. Jaberipur and B. Parhami, “Unified Approach to the Design of Modulo-(2n - 1) Adders Based on Signed-LSB Representation of Residues,” Proc. 19th IEEE Symp. Computer Arithmetic, pp. 57-64,(2009).
[10] H. T. Vergos and D. Bakalis, “On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components”(2008)
[11] R. Zimmerman, “Efficient VLSI Implementation of Modulo 2n 1 Addition and Multiplication,” Proc. 14th IEEE Symp. ComputerArithmetic, pp. 158-167, Apr. (1999).
[12] Singh, A., Anand, V., Singh, S., & Sharma, A. Examining GIS Methodologies and Their Diverse Applications in Solid Waste Management. Journal of Survey in Fisheries Sciences, 10(1), 1442-1447. (2023)
Published
2024-11-08
How to Cite
Pratik M, & Dinesh Sethi. (2024). FPGA Implementation of Modulo 2n ±1 Adder-Subtractor. Revista Electronica De Veterinaria, 25(2), 1487-1490. https://doi.org/10.69980/redvet.v25i2.1861
Section
Articles
