Pratik M, and Dinesh Sethi. “FPGA Implementation of Modulo 2n ±1 Adder-Subtractor”. Revista Electronica de Veterinaria 25, no. 2 (November 8, 2024): 1487-1490. Accessed June 2, 2026. https://www.veterinaria.org/index.php/REDVET/article/view/1861.